With the continuous development of semiconductor technology, the development trend of semiconductor process node following Moore's law continues to decrease. To adapt to the reduction of the process node, channel length of metal-oxide-semiconductor field-effect transistor (MOSFET) has to be shortened. The reduction of the channel length has advantages of increasing the core density of the chip and the switching speed of the MOSFET, etc.
However, the distance between a source region and a drain region of a device is shortened accordingly as the channel length of the device reduces. Therefore, control ability of a gate to the channel is degraded, and it is more and more difficult to pinch off the channel by the gate voltage. As a result, a subthreshold leakage phenomenon, also known as a short-channel effect (SCE), is more likely to occur.
Therefore, to better meet the requirements of scaling down the device size, the semiconductor process gradually began to transition from a planar MOSFET to a three-dimensional transistor having higher efficiency, such as a fin field effect transistor (FinFET). In the FinFET, the gate can control the ultrathin body (fin portion) from at least two sides. Thus, the FinFET has a much stronger gate-to-channel control ability than the planar MOSFET device, and can well suppress the short-channel effect. Compared to other devices, the FinFET has better compatibility with existing integrated circuit fabrication techniques.
However, the performance of the FinFET formed by the existing techniques needs to be improved. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.